Q.ANT Puts Photonic AI Chip Into Customers' Hands Via IONOS Pilot
Q.ANT's free closed beta puts second-generation photonic NPUs on IONOS bare-metal servers in Germany, testing claimed gains of up to 50x speed and big parameter cuts on real customer workloads.
By Amara Osei
3 min read

What's News
- Q.ANT opened a free closed-beta pilot on November 9, 2026 for its second-generation photonic processor on IONOS bare-metal servers in Germany.
- Q.ANT's pilot page reports 40% fewer parameters for image processing and 65% fewer for time-series prediction at the same accuracy.
- Leibniz Supercomputing Centre's April 21, 2026 evaluation found second-generation NPUs up to 50 times faster, with power consumption down 50-84% for typical HPC workloads.
- IONOS became Q.ANT's first commercial customer for the Native Processing Server under a May 19, 2026 agreement.
- LRZ researchers estimate the chips could be ready for AI-cluster deployment after one or two further development cycles.
By Amara Osei
Q.ANT is letting selected applicants test their own AI workloads on its second-generation photonic processor through dedicated IONOS bare-metal servers in Germany, the company announced on November 9, 2026. The free closed-beta pilot aims to find commercial uses for optical AI hardware. IONOS manually provisions each system, giving users SSH root access and an optional KVM console.
The program isn't open to everyone. Q.ANT limits participation to applicants with a concrete use case and enough expertise to administer a bare-metal server on their own. The pilot documentation describes the hosting as ISO 27001-certified, GDPR-compliant and sovereign within the EU.
From simulation to physical hardware
The pilot extends a development path Q.ANT started with its open-source software development kit on September 23, 2026. That SDK shipped programming interfaces for C and Python, sample applications, documentation and a CPU-based simulation backend. The new program moves approved users from simulation onto physical Native Processing Units (NPUs). Q.ANT provides drivers, its software stack and PyTorch integration; model and framework compatibility gets settled during onboarding.
The NPU executes nonlinear functions directly in the optical domain instead of decomposing them into long sequences of digital steps on conventional transistor-based chips. Q.ANT says this yields comparable or better results with fewer parameters, operations and resources. Accepted workloads span:
- industrial vision
- time-series forecasting
- scientific simulation
- robotics
- large-language-model and foundation-model inference
- physical AI and world models
Q.ANT's pilot page reports 40% fewer parameters for image processing and 65% fewer for time-series prediction at the same accuracy. The closed beta exists to test those numbers against users' own data and software.
How does the evaluation work?
After an application review and a video call, participants receive tutorials, code samples and documentation. That's followed by workload reviews and adjustments to the test focus. A final workshop examines energy and performance metrics, suitability for production and a possible next phase.
Participants keep ownership of their workloads, data and results, and everything stays confidential. Only aggregated, anonymized insights from discussions feed into Q.ANT's processor and platform development.
The pilot builds on the May 19, 2026 commercial agreement that made IONOS the first commercial customer for Q.ANT's Native Processing Server. Q.ANT positions the NPU as a co-processor for specific AI workloads alongside CPUs and GPUs — not a wholesale GPU replacement. The closed beta adds customer-run evaluation to an existing commercial relationship rather than introducing the partnership itself.
What do independent tests show?
An April 21, 2026 evaluation by the Leibniz Supercomputing Centre (LRZ) provides a separate reference point. LRZ tested both NPU generations on AI and high-performance computing tasks. It reported second-generation chips running up to 50 times faster in the best case, with a 25-fold acceleration in image recognition using a convolutional neural network. For typical HPC workloads, power consumption fell by roughly 50% to 84% from the first to second generation, depending on computational complexity.
The evaluation also flagged limits that matter for the pilot. The co-processors can't perform every operation optically and must exchange data continuously with classical processors. Energy efficiency peaks when computations stay on the optical unit, which makes data movement a central design constraint. The analog system converts data at 16-bit precision and must account for photodetector noise. More precise results require splitting complex tasks into multiple operations and more sophisticated software tools. LRZ researchers estimated the chips could be ready for AI-cluster deployment after one or two further development cycles.
The pilot now puts those questions in customers' hands. Whether the reported gains survive real workloads, data movement and software constraints will determine where photonic co-processing fits beside CPUs and GPUs in production AI infrastructure.
Source: unite.ai
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Senior reporter covering companies, deals and strategy in entrepreneurship, startups and venture funding at Business Bearings.
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