Expedera and Cadence Validate Combined Edge AI Subsystem in Simulation

By Grace Kim

Expedera paired its Origin Evolution neural processing unit IP with Cadence's Tensilica NeuroEdge 130 AI Co-Processor in a pre-silicon simulation, the company announced on November 9, 2026, demonstrating how the two semiconductor IP blocks divide and execute AI inference workloads.

Expedera called the result a validated pre-silicon integration — not a customer-silicon benchmark. The combined subsystem targets better performance and power efficiency with lower latency, cost and complexity, though the announcement supplies no combined measurements for those goals. The companies aim at inference designs across edge nodes, smartphones, automotive systems and data centers, and the approach can extend to other Tensilica digital signal processors.

Who said what?

Sharad Chole, Expedera's chief scientist, said models are running on the combined subsystem and that agentic AI workflows help the company deliver customized IP faster, giving customers "a faster, lower-risk path to production edge AI tailored to their performance and power requirements."

Amol Borkar, group director of product management and marketing for Cadence's Tensilica Products Group, said the co-processor assists Expedera's NPU with pre-processing, post-processing and operator fallback while also executing AI networks. That creates a real division of labor inside the subsystem rather than two accelerators running identical tasks.

How do the two blocks split the work?

Cadence designed NeuroEdge 130 to work alongside its own Neo NPUs, customer-developed NPUs or third-party NPU IP — and the Expedera pairing is a concrete example of that third-party route. Product documentation describes an Xtensa-based architecture using very long instruction word (VLIW) and single instruction, multiple data (SIMD) techniques, with optimized instructions for operations such as sigmoid, tanh and ReLU that suit NPUs poorly.

The NeuroEdge 130 can also issue instructions and commands to an NPU as a control processor, adding programmability for workloads nobody anticipated when the subsystem was designed. It connects through AXI or Cadence's High Bandwidth Direct Interface. The NeuroWeave software development kit, built on the Tensor Virtual Machine stack, tunes, optimizes and deploys models on Cadence AI IP.

Origin Evolution works differently: it breaks neural networks into packets — contiguous fragments — and routes them through Feed Forward, Attention and Vector processing blocks. Those blocks handle varying operations, data types and precisions, and the NPU supports LLMs, CNNs, RNNs and custom or black-box layers. The packet design cuts large memory movements while letting different kinds of network work share one architecture.

What do the earlier launch numbers show?

Origin Evolution debuted on May 20, 2025, available, production-ready and silicon-proven in customer production designs. Its launch figures cover the NPU alone:

• Scalability to 128 TFLOPS in one core, petaFLOPS and beyond with multiple cores
• More than 75% fewer external memory moves for Llama 3.2 1B and Qwen2 1.5B versus alternative solutions

Cadence introduced NeuroEdge 130 on May 7, 2025, with general availability and ISO 26262-ready status for automotive applications. Cadence reported more than 30% area savings and over 20% lower dynamic power and energy at performance comparable to Tensilica Vision DSPs on AI networks and operators. Those numbers compare the co-processor with Cadence's own Vision DSPs; they don't measure the new Expedera-Cadence subsystem.

For edge SoC designers, the announcement offers a validated integration path between two existing IP families: Expedera's packet-based acceleration plus Cadence's programmable handling of surrounding operators and unforeseen workloads. It addresses a practical tension in edge inference — dense-math acceleration versus flexibility for changing models — inside a subsystem configurable for different performance and power targets. What it doesn't yet offer is silicon-level proof, so expect the real test when a customer tape-out runs the pair in actual hardware.