MemryX Targets 10x Compute Jump With MX3+ Edge AI Chip

MemryX has set design targets of up to 10 times more peak AI compute and nearly 10 times more on-chip memory for its MX3+ inference accelerator, announced November 10, 2026. The fabless chipmaker claims it can hit those numbers while staying inside the same low-power operating envelope as its current MX3 part.

The math is stark. Today's MX3 delivers 6.25 TFLOPS of AI compute and 10.5 MB of on-chip weight memory per chip, drawing between 200 mW and 3 W. MX3+ promises roughly ten times the compute and model-weight capacity of that part without expanding its silicon footprint. MemryX says the design addresses board-space and system-cost constraints as well as power, since the chip is meant to drop into the same physical and thermal budgets its predecessor occupied.

The figures are targets, not shipping specifications. The current MX3 is available for volume orders now; MX3+ exists as a roadmap. MemryX must still produce and validate the new hardware before any announced number holds.

What workloads does MX3+ aim at?

MemryX is pointing the device at larger and more complex models than the MX3 can carry. Planned workloads include:

• higher-resolution vision
• transformer-based models
• small language models
• vision-language-action models
• hybrid architectures
• more sophisticated multi-model pipelines

Target deployments span industrial automation, robotics, intelligent transportation, smart infrastructure, video management, healthcare devices, retail and consumer electronics. That is a broad list, but it maps to one commercial logic: run bigger models at the edge without moving inference to the cloud or paying for a bigger power supply.

How does multi-chip scaling work?

Configurations will scale from one MX3+ to 16 chips operating as a unified logical device. MemryX says the 16-chip configuration is designed to deliver more than 1 POPS — one peta-operation per second — of peak AI compute and 2.16 GB of distributed on-chip memory.

The mechanism matters as much as the figure. Distributed dataflow lets the accelerators work together without the host processor managing individual chips. The MemryX Neural Compiler automatically maps neural networks across the available accelerators, so developers scale performance without manually partitioning their models.

MX3+ pairs the added on-chip memory with near-memory, pipelined processing that keeps model data close to computation and minimizes data movement. MemryX says the design targets larger models and higher-resolution inputs while maintaining predictable, low-latency inference at batch size one — the regime that matters for real-time edge systems like cameras and robots.

The existing MX3 datasheet documents the same scaling ceiling: host offload over PCIe or USB, support for x86, Arm and RISC-V processors, and PCIe cascading of up to 16 chips through a single host interface. MX3+ retains that multi-chip approach and a familiar development workflow.

What did the CEO say?

President and CEO Ross Jatou said MemryX expects the shared architecture to provide one development-to-production path across embedded, industrial and high-density systems and to significantly lower total cost of ownership for high-density edge deployments.

That single-path argument is the commercial pitch. Customers who validated models on MX3 hardware keep their toolchain as they move up, and the compiler absorbs the complexity of spreading a model across more chips.

When will hardware actually ship?

Not soon. MemryX is accepting early-access requests from selected strategic partners and enterprise customers to co-validate pre-production hardware and software. Engineering samples are targeted for late 2027, with volume production planned for mid-2028. Further specifications, configurations and availability details will come as development progresses.

The company also says new capabilities in MX3+ will carry into MX4, its future platform for advanced multimodal and large-language-model inference. The official MX4 product page adds advanced vision and generative AI to its target workloads and sets availability in 2029.

The immediate work is validation rather than deployment. Early-access systems will need to show that the compute and memory gains can coexist with MX3's power and footprint constraints while preserving compiler-led scaling and predictable low-latency inference — the constraint that has sunk many edge AI roadmaps before this one.